Sense amplifier circuit

ABSTRACT

In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

BACKGROUND OF THE INVENTION

This invention relates to a sense amplifier circuit used in dynamic RAM,static RAM, etc.

A conventional latch type sense amplifier circuit is explained byreferring to FIGS. 1 and 2. FIG. 1 is an equivalent circuit diagram of aconventional latch type sense amplifier circuit, in which numerals 100and 200 are respectively first N-type transistor (hereinafter calledT100) and second N-type transistor (T200) Numerals 3 and 5 are bit wirepair, and 4 is an earth wire. In the equivalent circuit shown in FIG. 1,the operation of amplifying the potential difference V of the bit wire 3and bit wire 5 by the sense amplifier circuit is as follows. First,taking notice of T100 and T200, since the sources are commonly connectedto the earth wire, the difference between the gate-source voltageapplied to T100 (hereinafter called V_(gs1)) and the gate-source voltageapplied to T200 (V_(gs2)) is as expressed below:

ΔV=|V_(gs1)−V_(gs2)| . . .   (1)

That is, the potential difference of bit wire pair 3, 5 is thedifference of the gate-source voltage applied to T₁₀₀, T₂₀₀, which isalso the difference of currents i₁₀₀, i₂₀₀ flowing in T₁₀₀, T₂₀₀. As thecurrents i₁₀₀, i₂₀₀ flow, since these are discharge currents fordischarging the electric charge of the bit wires to the earth wire, thepotential of bit wire 3 V_(bit) and the potential of bit wire 5 V_(bit)decrease by the portions shown below. $\begin{matrix}{{\Delta \quad V_{bit}} = \frac{i_{1} \cdot t}{c_{3}}} & (2)\end{matrix}$

$\begin{matrix}{{\Delta \quad V_{bit}} = \frac{i_{2} \cdot t}{c_{5}}} & (3)\end{matrix}$

where t is the discharge time, and c₃, c₅ are capacities of bit wires.From the relationship of equations (1), (2), (3), and the relation ofΔV_(bit)=ΔV_(gs2), ΔV_(bit)=V_(gs1), evidently a positive feedback isapplied to the potential difference of the bit wire pair 3, 5, and thepotential difference is amplified.

One of the important factors to determine the performance of the senseamplifier operating in such manner is the sensitivity. This is to showthe smallest limit of potential difference that can be amplifiedcorrectly, and the minimum potential difference is called thesensitivity. As stated above, the potential difference of the bit wirepair is the gate-source voltage of MOS transistors T₁₀₀, T₂₀₀ and alsobecomes the potential difference flowing in the transistors, and thispotential difference expands the potential difference of bit wire pair,and hence the following point is important. The point is whether thesmall gate-source voltage difference (the difference of V_(gs1) andV_(gs2)) is correctly obtained as the difference of currents (thedifference of i₁₀₀ and i₂₀₀) or not. That is, if V_(gs1)>V_(gs2),however small the difference may be, the relation of i₁₀₀>i₂₀₀ must besatisfied. To realize this, it is necessary that the threshold voltageand drivabilities gm of MOS transistors T₁₀₀, T₂₀₀ be exactly the same.

In order to realize such relations, conventionally, a sense amplifiercircuit was realized in the wiring and layout as shown in FIG. 2. Thisis a layout drawing of an actual sense amplifier circuit. This layout isreplaced by an equivalent circuit diagram in FIG. 1. As evident fromthis drawing, the currents i₁₀₀, i₂₀₀ flow in the reverse directionsgeometrically on the wafer, that is, a semiconductor integrated circuitboard.

The sense amplifier circuit of N-type MOS transistors was explained inFIGS. 1 and 2, but the P-type configuration is exactly the same exceptthat the earth wire 4 is Vcc wire, that the MOS transistors 100, 200 areP-type MOS transistors, and that the current directions of both i₁₀₀ andi₂₀₀ are reverse.

However, in the sense amplifier circuit as shown in FIGS. 1, 2, thefollowing problems exist because the current i₁₀₀ flowing in the MOStransistor T₁₀₀ and the current i₂₀₀ flowing in the MOS transistor T₂₀₀are opposite.

First of all, generally, when forming source and drain of MOStransistor, the ion beam is designed to reach the wafer at a certainangle in order to prevent channeling of ions. Therefore, the overlappingamount of the gate electrode and source region or drain region isasymmetric in the source region and drain region. This tendency becomesmore obvious when the angle of the ion beam is deviated more from theangle perpendicular to the wafer surface, or the ratio of thickness towidth of gate electrode (aspect ratio=thickness/width) becomes larger.This asymmetricity is considered to be caused, aside from the formationof source and drain, by injection of ions for channel stop of source anddrain, asymmetricity of shape of the gate electrode to become injectionmask, and asymmetricity of the shape of gate side oxide spacer. Thistendency is considered to be intensified as the gate length and gatewidth becomes smaller, and this problem is a must to be solved in thefine MOS transistors used in large-scale integrated circuit.

Incidentally, when asymmetricity occurs in the ion injection quantity ofsource and drain, another asymmetricity will naturally occur in thecurrent-voltage characteristic. In other words even in a sametransistor, the threshold voltage and drivability gm come to havedifferent values depending on the direction of the flowing current.Thus, as explained in the prior art, in the sense amplifier circuit asshown in FIG. 1, even if it is designed so that the T₁₀₀ and T₂₀₀ mayhave identical threshold voltage and drivability gm, since thedirections of the flowing currents are reverse, it is possible, owing tothe asymmetricity of the current-voltage characteristic, that thedischarge current may be possibly greater in the current i₂₀₀ flowing inT₂₀₀ than the current i₁₀₀ flowing in T₁₀₀ if the drivability gm isgreater in T₂₀₀ than in T₂₀₀ although the gate voltage V_(gs1) of T₁₀₀is greater than gate voltage V_(gs2) of T₂₀₀. Therefore, the smallpotential difference of the bit wire pair 3, 5 is not amplifiedcorrectly, and the potential of the bit wire 5 giving V_(gs1) is smallerthan the potential of the bit wire 3 giving V_(gs2), and the senseamplifier circuit may malfunction.

By the sensitivity S of the sense amplifier and reading from the memorycell, the difference from the potential difference ΔV occurring in thebit wire pair 3, 5, that is, M in M=ΔΔV−S, is called a margin. The valueof M seems to be much smaller because the reading voltage ΔV tends to besmaller along with the increase of bit wire capacity and decrease ofcell capacity by high integration of memory cell. Hence, highersensitivity of the sense amplifier circuit is more and more needed. Itis therefore important to equalize the threshold voltage and drivabilitygm of the transistor or pair T₁₀₀, T₂₀₀ of the sense amplifier circuit,in consideration of the current direction. In the conventional senseamplifier circuit and layout, however, since the current directions ofT₁₀₀, T₂₀₀ are opposite, the asymmetricity of the current-voltagecharacteristic due to asymmetricity of feeding amounts of source anddrain has a considerable effect, and the sensitivity of the senseamplifier tends to worsen.

SUMMARY OF THE INVENTION

It is hence a primary object of this invention to present a highsensitivity sense amplifier circuit capable of suppressing theasymmetricity of the current-voltage characteristic of transistor paircomposing the sense amplifier.

To achieve the above object, the sense amplifier circuit of thisinvention is composed by coupling the first bit wire coupled to thememory cell and the drain part of first MOS transistor, coupling thesecond bit wire making a pair with the first bit wire and the gate partof the first MOS transistor, coupling the drain part of second MOStransistor and the second bit wire, coupling the gate part of the secondMOS transistor and the first bit wire, coupling the source parts of thefirst and second MOS transistors commonly to a power source wire, andforming both first MOS transistor and second MOS transistor, out of theN-type of P-type MOS transistors composing the latch type senseamplifier circuit, by a plurality of N-type or P-type MOS transistorsconnected in series.

While the novel features of the invention are set forth in the appendedclaims, the invention both as to organization and content, will bebetter understood and appreciated, along with other objects and featuresthereof, from the following detailed description taken in conjunctionwith the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram of a conventional senseamplifier;

FIG. 2 is a mask pattern showing the layout of the same circuit;

FIG. 3 is an equivalent circuit diagram of a sense amplifier circuit ina first embodiment of this invention;

FIG. 4 is a mask pattern diagram showing the layout of the same circuit.

FIG. 5(a-b) is a diagram comparing the imbalance of the transistor pairin this invention with the imbalance of the transistor pair in the priorart as indicated by measured values; and

FIG. 6 is a mask pattern diagram showing the layout of a secondembodiment of this invention.

DETAILED DESCRIPTION OF THE INVENTION

Of the two N-type MOS transistor circuits making up a pair to compose asense amplifier circuit, both first MOS transistor circuit and secondMOS transistor circuit are composed of N-type MOS transistors connectedparallel in an even number of stages, and the discharge current flowingin the earth wire from the parallel connection circuit of an even numberof stages composing the first MOS transistor is presented by the evennumber of stages. These currents are supposed to be i₁₁, i₁₂, i₁₃,....., i_(1n). Similarly, the discharge currents flowing in the earthwire from the parallel connection circuit of an even number of stagescomposing the second MOS transistor circuit are i₂₁, i₂₂, i₂₃, .....,i_(2n). Here n is an even number.

Supposing, for example, n=2, i₁₁ and i₁₂ are the currents flowing in thefirst MOS transistor circuit, and the sum of the currents flowing frombit wires into the earth wire is i₁₁+i₁₂. Likewise, the currents flowingin the second MOS transistor circuit is i₂₁ and i₂₃, and the sum of thecurrents flowing from the bit wires into the earth wire is i₂₁+i₂₂. Thegeometrical relation of current directions of il_(l), i₁₂, i₂₁, i₂₂ onthe wafer, that is, the semiconductor circuit board is as follows.

i₁₁ and i₂₂ are in same direction . . .   (4)

i₁₂ and i₂₁ are in same direction . . .   (5) $\begin{matrix}{\begin{pmatrix}{i_{11}\quad {and}\quad i_{12}} \\{i_{22}\quad {and}\quad i_{22}}\end{pmatrix}\quad {are}\quad {in}\quad {opposite}\quad {directions}} & (6)\end{matrix}$

From the relation of (4), (5), (6), if the threshold voltage anddrivability gm become asymmetric due to the current direction because ofthe asymmetricity of source and drain, when (i₁₁+i₁₂) and (₂₁+i₂₂) arecompared, if asymmetricity of i₁₁ and i₂₁, and assymetricity of i₁₂ andi₂₂ should occur, they are canceled to null on the whole.

Thus, if the first MOS transistor and second MOS transistor circuits areboth composed in parallel connection of an even number of stages, ifthere is asymmetricity in one pair of transistors, the asymmetricity iscanceled to null in the even number pair of transistors.

FIG. 3 and FIG. 4 show an equivalent circuit and its layout diagram of asense amplifier circuit in one of the embodiments of this invention.

First relating to the equivalent circuit diagram of the sense amplifiercircuit shown in FIG. 3, numerals 1, 2 are first N-type MOS transistorcircuits connected in parallel 6, 7 are second N-type MOS transistorcircuits connected in parallel, and these first and second N-type MOStransistor circuits are making up a transistor pair. Numerals 3, 5 arebit wire pair, and 4 is an earth wire. FIG. 4 shows a mask drawing of anactual layout of the circuit diagram of sense amplifier shown in FIG. 3,that is, a semiconductor integrated circuit pattern formed on asemiconductor substrate. Numeral 10 is an aluminum used in wiring, and11 is a polysilicon used in gate electrode, 12 is a contact region forconnecting the drain region of MOS transistors 1, 2 and bit wire 3, 13is an active region of transistor in oxide definition (OD), that is, aninseparate region, 50 is a contact region of gate electrode of MOStransistors 1, 2 and bit wire 5, 51 is a contact region for connectingthe common source region of MOS transistors 1, 2 and 3, 4, and earthwire 4, 53 is a contact region for connecting the drain region of MOStransistors 6, 7, and bit wire 5, 60 is a contact region for connectinggate electrode of MOS transistors 6, 7 and bit wire 3, and 42 is amemory cell region disposed at both sides of the sense amplifiercircuit, 40 being word wire and 41 being memory cell.

In FIG. 3, the bit wires 70, 71 in the left side memory cell region areconnected to bit wires 3, 5, respectively. But the wires 72, 73 in theright side memory cell are not connected to 3, 5.

Regarding the currents in the sense amplifier circuit, as shown in FIG.3, currents flowing in transistors 1, 2, 6, 7 (hereinafter called T₁,T₂, T₆, T₇) are considered. The current i₁ flowing in T₁ and the currenti₃ flowing in T₃ are geometrically same in direction on the wafer, andthe i₂ flowing in T₂ and the current i₄ flowing in T₄ are same indirection. The transistors 1, 2, 6, 7 are designed to have same channellength and channel width, and the manufacturing conditions are alsosame. Accordingly, the current-voltage characteristics of transistors 1,2, 6, 7 are considered to show an asymmetricity, of source and drain,that is, same characteristics except in the geometrical currentdirection of the wafer.

The effects of this embodiment are described below.

In the embodiment of this invention shown in FIGS. 3, 4, taking note ofthe sum of currents (i₁+i₂) flowing in T₁, T₂ composing the first N-typeMOS transistor circuit of the transistor pair of the sense amplifiercircuit, and the sum of currents (i₃+i₄) flowing in T₃, T₄ composing thesecond N-type MOS transistor circuit, i₁ and i₃ are currents in the samedirection, and same characteristics are shown. Besides, since i₂ and i₄are same in direction, it is considered that same characteristics areshown, and the entire current-voltage characteristics, that is, thecurrent-voltage characteristics of (i₁+i₂) and (i₃+i₄) are canceled inthe asymmetricity due to current direction and are considered to havesame characteristics, which makes it possible to enhance the sensitivityof sense amplifier circuit.

According to this invention, since both the first and second MOStransistors of the N-type or P-type MOS transistor pair to compose alatch type sense amplifier circuit are made of N-type or P-type MOStransistors connected parallel in an even number of stages, wheneven-number currents flowing in the first MOS transistor circuit and theeven-number currents flowing in the second MOS transistor circuit arecompared, the current geometrically in the same direction of the waferas the current flowing in the first MOS transistor circuit flows also inthe second MOS transistor circuit, and therefore, on the whole, thecurrent-voltage characteristics of the sum of currents flowing in thefirst MOS transistor circuit and the sum of currents flowing in thesecond MOS transistor circuit are canceled in the asymmetricity due tothe direction of individual currents to become identical incharacteristics, so that the sensitivity of the sense amplifier circuitmay be increased.

FIG. 5 shows the asymmetricity of the current-voltage characteristic ofthe transistor pair composing a sense amplifier circuit experimentallyfabrication in order to verify this invention, in which (a) shows theasymmetricity of threshold voltage, and (b) indicates the asymmetricityof drain current. Here, the asymmetricity is defined as follows.${{Asymmetricity}\text{:}\quad \Delta \quad {Vth}} = {\frac{{Vth}_{1} - {Vth}_{2}}{{Vth}_{1}} \times 100\%}$$\quad {{\Delta \quad {Ids}} = {\frac{{Ids}_{1} - {Ids}_{2}}{{Ids}_{1}} \times 100\quad \%}}$

where ΔVth is the asymmetricity of threshold voltage, ΔIds in theasymmetricity of drain current, Vth₁, Vth₂ are threshold voltage of pairtransistors, and Ids₁, Ids₂ are drain currents of pair transistors.

In diagrams (a) and (b), S is a series connection which corresponds tothe prior art, and P is a parallel connection which corresponds to thetransistor pair characteristic of this invention. Whether the transistorgate width W is 2μ or 1 μ, and if the gate length is in a range of 0.5to 1.0 μm, it is known that the asymmetricity of transistor pair in thisinvention is obviously small. This is because of the reason statedabove, and it proves the efficacy of this invention.

A second embodiment is shown in FIG. 6, in which 4is an earth wire madeof aluminum (AL), 20, 21, 30, 3 1 are bit wires made of polycide (PB),13 is OD (oxide definition inseparable region), 12 is a contact betweenAL and OD, and 14 is a contact between PB and OD.

The features of the sense amplifier circuit shown in this drawinginclude, aside from the composition of transistor pair for composing thesense amplifier circuit by transistors connected parallel in an evennumber of stages (two stages) same as in the first embodiment, thecontinuity of the inseparable region OD to form transistors, without anintervening separate region, in the bit wire arranging direction, thatis, in the column direction. This is realized because the common sourceregion of the transistor pair adjacent in the column direction, that is,the OD region having the earth wire 4 connected by means of contact 12is shared by the transistor pair adjacent at both sides in the columndirection. By this configuration, the separate region between thetransistor pair adjacent in the column direction which was requiredconventionally is no longer necessary, and the layout area of the senseamplifier can be reduced. A further greater advantage is that the dropof yield of the sense amplifier circuit attributable to incompleteness(leak current) of separation of the transistor pair adjacent in a narrowlimited space can be reduced.

While specific embodiments of the invention have been illustrated anddescribed herein, it is realized that other modifications and changeswill occur to those skilled in the art. It is therefore to be understoodthat the appended claims are intended to cover all modifications andchanges as fall within the true spirit and scope of the invention.

We claim:
 1. A sense amplifier circuit comprising first and second bitwires coupled to a memory cell, a first MOS transistor having a drainconnected to said first bit wire, said second bit wire is coupled to thegate of the first MOS transistor, a second MOS transistor having a drainconnected to said second bit wire, and either an N-type a P-type MOStransistor pair to compose a latch type sense amplifier circuit bycoupling the gate of the second MOS transistor and the first bit wire,and coupling the sources of the first and second MOS transistorscommonly to a power source wire, wherein both first and second MOStransistors are composed of a plurality of either N-type or P-type MOStransistor connected in parallel.
 2. A sense amplifier circuit comprisesforming first and second MOS transistors of a transistor pair in thesame region as the first MOS transistor of the transistor pair at bothsides adjacent in the column direction, and also forming the second MOStransistor in the same region as the second MOS transistor of the pairof transistors at both sides adjacent in the column direction.
 3. Aplurality of sense amplifier circuits arranged along a column direction,each of said sense amplifier circuits comprising: at least one first MOStransistor and at least one second MOS transistor coupled to oneanother; wherein said first MOS transistor is formed in the samecontinuous region as other first MOS transistors of adjacent senseamplifier circuits on both sides of said first MOS transistor in thecolumn direction; and wherein said second MOS transistor is formed inthe same continuous region as other second MOS transistors of saidadjacent sense amplifier circuits on both sides of said second MOStransistor in column direction.
 4. The sense amplifier circuit of claim3, wherein said first MOS transistor comprises a plurality of MOStransistors connected in parallel.
 5. The sense amplifier circuit ofclaim 4, wherein said second MOS transistor comprises a plurality of MOStransistors connected in parallel.
 6. The sense amplifier circuit ofclaim 5, wherein each of said first and second MOS transistors consistsof an even number of MOS transistors.
 7. The sense amplifier circuit ofclaim 3, wherein said first and second MOS transistors are each formedin respective first and second common areas.
 8. The sense amplifiercircuit of claim 7, wherein said first MOS transistors located adjacentone another in said column direction are not electrically isolated fromone another.
 9. The sense amplifier circuit of claim 7, wherein saidsecond MOS transistors located adjacent one another in said columndirection are not electrically isolated from one another.
 10. The senseamplifier circuit of claim 7, wherein adjacent first MOS transistorshave sources that are commonly connected.
 11. The sense amplifiercircuit of claim 7, wherein adjacent second MOS transistors have sourcesthat are commonly connected.
 12. The sense amplifier circuit of claim 3,wherein each of said sense amplifier circuits is coupled on both sidesin the column direction to adjacent sense amplifier circuits by a commonsource.
 13. The sense amplifier circuit of claim 3, wherein each of saidfirst and second MOS transistors comprises first and second gateportions having a drain therebetween.
 14. The sense amplifier circuit ofclaim 13, wherein the direction of current flow in said first gateportion is opposite to the direction of current flow in said second gateportion.
 15. The sense amplifier circuit of claim 3, wherein a gate ofsaid at least one first MOS transistor is coupled to a drain of said atleast one second MOS transistor.
 16. The sense amplifier circuit ofclaim 3, wherein a source of said at least one first MOS transistor iscoupled to a source of said at least one second MOS transistor.
 17. Aplurality of sense amplifier circuits arranged along a column direction,each of said sense amplifier circuits comprising: first and second MOStransistors each formed from a transistor pair having commonly connectedgates, commonly connected sources, and commonly connected drains;wherein said first MOS transistor is formed in the same continuousregion as other first MOS transistors of adjacent sense amplifiercircuits on both sides of said first MOS transistor in the columndirection; and wherein said second MOS transistor is formed in the samecontinuous region as other second MOS transistors of said adjacent senseamplifier circuits on both sides of said second MOS transistor in thecolumn direction.
 18. The sense amplifier circuit of claim 17, whereinthe direction of current flow in one of the transistors of eachtransistor pair is opposite to the direction of current flow in theother transistor of said transistor pair.
 19. The sense amplifiercircuit of claim 17, wherein said sources of said first MOS transistorare connected to said sources of said second MOS transistor.
 20. Thesense amplifier circuit of claim 19, further comprising first and secondbit wires coupled to said first and second MOS transistors.
 21. Thesense amplifier circuit of claim 20, wherein said first bit wire isconnected to said drains of said first MOS transistor.
 22. The senseamplifier circuit of claim 21, wherein said first bit wire is connectedto said gates of said second MOS transistor.
 23. The sense amplifiercircuit of claim 22, wherein said second bit wire is connected to saidgates of said first MOS transistor.
 24. The sense amplifier circuit ofclaim 23, wherein said second bit wire is connected to said drains ofsaid second MOS transistor.
 25. A latch type sense amplifier circuitcomprising: first and second bit wires each coupled to a memory cell;first and second MOS transistors each consisting of an even number ofeither N-type or P-type MOS transistors connected in parallel to eachother; said first MOS transistor having drains connected to said firstbit wire and gates connected to said second bit wire; said second MOStransistor having drains coupled to said second bit wire and gatesconnected to said first bit wire; and said first and second MOStransistors having sources commonly connected to a power source wire.26. The latch type sense amplifier circuit of claim 25 wherein saidfirst and second MOS transistors each consists of two N-type or P-typeMOS transistors connected in parallel.
 27. The latch type senseamplifier circuit of claim 25 wherein said first and second MOStransistors each consist of an even number of N-type transistors andsaid power source wire is an earth wire.
 28. The latch type senseamplifier circuit of claim 25 wherein said first and second MOStransistors each consist of an even number of P-type transistors andsaid power source wire is a Vcc wire.